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TDA7421N
AM/FM TUNER FOR CAR RADIO AND HI-FI APPLICATIONS
PRELIMINARY DATA
s s s s s s s s
HIGH PERFORMANCE FRONT-END IC FOR AM/FM RECEIVERS FULLY INTEGRATED HIGH-SPEED PLL FOR OPTIMIZED RDS APPLICATIONS FM MPX/AM AUDIO OUTPUT, 450kHz AM IF OUTPUT FOR STEREO AM APPLICATIONS AM DOUBLE CONVERSION ARCHITECTURE AM/FM STATION DETECTOR AND DIGITAL IF-COUNTER SINGLE FREQUENCY REFERENCE FOR BOTH AM AND FM FULL ELECTRICAL ADJUSTMENT I2C-BUS PROGRAMMABLE
TQFP64 ORDERING NUMBER: TDA7421N
DESCRIPTION The TDA7421N is a high-performance tuner circuit which integrates AM and FM sections, PLL frequency sinthesizer and IF counter on a single chip. Use of BICMOS technology allows the implementation of tuning functions with a minimum of external components.Value spread of external components can be fully compensated by means of on-chip elecPIN CONNECTIONS
AM AGC1 RF AMP
trical adjustment controlled by external P. The FM quality detection circuit, in conjunction with the digital IF counter, enables the stop-station function in "seek" mode and MPX mute during reception. The combination of programmable level detector and IF counter allows reliable AM stop-station performance. The Automatic Gain Control (AGC) operates on different signal bandwidths in order to optimize sensitivity and dynamic range. I2C-bus controls functions such as AGC, amplifier gains, PLL and counter settings.
FM IF AMP1 OUT
FM IF AMP1 IN +
FM IF AMP2 IN +
AM SMETER TC
FM IF AMP1 IN -
AM AGC1 PIN
AM AGC1 TC
MIX OUT +
MIX OUT -
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AM MIX1 IN AM MIX1 IN + FM MIX IN FM MIX IN + FM RF AGC IN FM AGC OUT RF GND VCO B VCO E OSC GND XTAL D XTAL G OSC VCC FM ANT ADJ FM RF ADJ PLL VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DIG GND IFC SSTOP AM STEREO OUT CLN GND IF2 GND AM AGC2 TC PLL GND PLL VREF DIG VDD AM DET SLEEP SDA LP OUT LP IN1 LP IN2 LP IN3 SCL 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 FM IF AMP2 OUT IF1 VCC FM LIM IN + FM LIM IN IF1 GND FM BW TC FM MUTE DRIVE FM SMETER AM SMETER FM DET ADJ FM SD AM SD AUDIO OUT FM QUAD+ FM QUADIF2 VCC AM IF2 IN AM REF AM BPF
FM IF AMP2 IN D98AU909
August 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
AM MIX2 OUT
FM IF AGC IN
AM MIX2 IN +
AM MIX2 IN-
RF VCC
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MIX OUT-
MIX OUT+
FM IF AGC IN
FM IF AMP1 IN-
FM IF AMP1 IN+
FM IF AMP1 OUT
FM IF AMP2 IN-
FM IF AMP2 IN+
FM IF AMP2 OUT
LIM IN-
LIM IN+
VCO
AM IF2 IN
AM IFREF
AM AGCI TC
AM MIX2 IN+
AM MIX2 IN-
AM MIX2 OUT-
AM BPF
2/38
IFC SSTOP AM STEREO OUT QUAD+ QUADFM MUTE AM IF FM AGC AM IF COUNT FM IF COUNTER AM AM SMETER FM SMETER FM DET ADJ OUT QUADRATURE DETECTOR FM AUDIO OUT FILTER ADJ. SLIDER LIMITER AM SMETER STOP STATION S METER DETUNING DETECTOR SOFT MUTE DETUNING MUTE FM SD AM SD/ FM SD AM SD BW TC TRIPLE OUT
TDA7421N
BLOCK DIAGRAM
FM AGC OUT
FM RF AGC IN
FILTER ADJ.
FM MIX IN+
FM MIX IN-
/
PHASE COMPARATOR
VCOE ADJACENT CH. MUTE LPIN2 LPIN1 LPIN3
VCOB 10.25MHz OSC ADJACENT CH. DET.
XTALG
/
XTALD
/
4 BIT DAC
+
4 BIT DAC
FM ANT ADJ
+
+
AM MIX INAM RF AGC LOCK DET CHARGE PUMP
FM RF ADJ LPOUT PLL VCC
-
AM MIX IN+ FILTER ADJ.
PLL VREF
AM AGC1 RF AMP OUT PLL GND AM IF AGC SMETER
AGC1 ANT
SDA SCL SLEEP I2C BUS
AM IF COUNTER
/
AM DETECTOR
AM SMETER TC
AM AGC2 TC
AM DET
D99AU1042
TDA7421N
ABSOLUTE MAXIMUM RATINGS
Symbol Tamb Tstg VCC VDD Parameter Operating Temperature Range Storage Temperature Range Analog Supply Voltages (PLL, RF, IF1, IF2, OSC) Digital Supply Voltage Value -40 to 85 -55 to 150 10.2 5.5 Unit C C V V
THERMAL DATA
Symbol Rth j-amb, fa Rth j-amb, sol Parameter Thermal Resistance Junction-Ambient, Free Air Thermal Resistance Junction-Ambient, Soldered Typ. Value 68 55 Unit C/W C/W
PIN DESCRIPTION
N. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Name AM MIX1 IN AM MIX1 IN + FM MIX1 IN FM MIX1 IN + FM RF AGC IN FM AGC OUT RF GND VCO B VCO E OSC GND XTAL D XTAL G OSC VCC FM ANT ADJ FM RF ADJ PLL VCC LP OUT LP IN1 LP IN2 Function AM 1st mixer negative input (differential -) AM 1st mixer positive input (differential +) FM mixer negative input (differential -) FM mixer positive input (differential +) RF AGC input FM AGC output voltage RF ground Local oscillator input to the transistor base Local oscillator input to the transistor emitter Oscillator ground Crystal oscillator MOS amplifier output Crystal oscillator MOS amplifier input Oscillator positive supply Tuning varicap voltage for antenna FM filter Tuning varicap voltage for RF FM filter PLL positive supply Op Amp output to PLL loop filters FM loop filter connection to op-amp inverting input AM loop filter connection to op-amp inverting input
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TDA7421N
PIN DESCRIPTION (Continued)
N. 20 21 22 23 24 25 26 27 28 (*) 29 30 31 32 33 34 35 36 37 38 39 40 (*) 41 (*) Name LP IN3 PLL VREF PLL GND SLEEP SDA SCL DIG VDD DIG GND IFC SSTOP AM STEREO OUT CLN GND IF2 GND AM AGC2 TC AM DET AM BPF AM REF AM IF2 in IF2 VCC FM QUAD FM QUAD + AUDIO OUT FM SD AM SD FM SMETER AM SMETER FM DET ADJ FM MUTE DRIVE FM BW TC IF1 GND FM LIM IN FM LIM IN + IF1 VCC FM IF AMP2 OUT Function FM-HS loop filter connection to op-amp inverting input Voltage reference to Op Amp noninverting input PLL ground I2C bus disconnect signal I2C bus data I2C bus clock Digital positive supply Digital ground IF-Counter stop signal or AM IF2 amplifier output "Clean" ground IF2 ground AM 2nd AGC time constant AM detector capacitor AM IF filter Reference voltage of AM IF amplifier AM IF2 amplifier input IF2 positive supply FM quadrature detector tank (differential -) FM quadrature detector tank (differential +) FM MPX/AM Audio output FM station detector output or AM station detector output FM S-meter output or AM S-meter output or FM detector adjustment output FM mute time constant FM detuning detector time constant IF1 ground FM limiter negative input (differential -) FM limiter negative input (differential +) IF1 positive supply FM 2nd IF amplifier output
42 43 44 45 46 47 48
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TDA7421N
PIN DESCRIPTION (Continued)
N. 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Name FM IF AMP2 IN FM IF AMP2 IN + FM IF AMP1 OUT FM IF AMP IN FM IF AMP IN + AM S-METER TC AM MIX2 OUT RF VCC AM MIX2 IN AM MIX2 IN + FM IF AGC IN MIX OUT MIX OUT + AM AGC1 TC AM AGC1 RF AMP AM AGC1 PIN Function FM 2nd IF amplifier negative input (differential -) FM 2nd IF amplifier positive input (differential +) FM 1st IF amplifier output FM 1st IF amplifier negative input (differential -) FM 1st IF amplifier positive input (differential +) AM S-meter time constant AM 2nd mixer output RF positive supply AM 2nd mixer negative input (differential -) AM 2nd mixer positive input (differential +) FM IF AGC input FM/AM 1st mixer negative output (differential -) FM/AM 1st mixer positive output (differential +) AM 1st AGC time constant AM 1st AGC voltage output (to RF amplifier) AM 1st AGC current output (to antenna attenuation diodes)
(*) Pin function is user defined by software.
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TDA7421N
FM SECTION GLOBAL PERFORMANCES Refer to Evaluation Circuit - Input 98.1MHz, 40KHz dev., 1KHz mod., 60dBV antenna level, mono. - MPX Output, de-enphasis 50s, BPF 200Hz-15KHz.
Symbol FM ICC S+N/N THD VO AF US1 US2 AGCSP Parameter Total Supply Current Including Mixer Signal to Noise Ratio Total Harmonic Distortion Audio Output Level Usable Sensitivity (40dB) Usable Sensitivity (26dB) AGC Starting point 75kHz Deviation antenna level at which S+N/N = 40dB antenna level at which S+N/N = 26dB Test Condition Min. Typ. 90 66 0.3 400 0 -6 55 Max. Unit mA dB % mVRMS dBV dBV dBV
AM SECTION GLOBAL PERFORMANCES
Refer to Evaluation Circuit - Input: fc = 999KHz, f mod = 400Hz, m = 30%, 74dBVemf antenna level unless otherwise specified. - Audio Output + RC BPF (BPF 20Hz - 20KHz) MICC VIN MIN VIN US Vis S+N/N IMAG Tw THD Total supply current including mixers Maximum Sensitivity Usable Sensitivity AGC Range Signal to Noise Ratio Image Rejection Tweet, (S+N/N) Total Harmonic Distortion m = 80% VINRF = 120dBVemf VAF VAMST Audio Output Level AM IF2 Output level VAF = - 20dB S+N/N = 20dB VAF = -10dB VINRF = 74dBu fim = 22.399MHz, antenna level @ VF = -10dB f1 = 900KHz;f2 = 1350KHz 1.2 0.3 1 0.3 107 105 80 13 27 50 54 mA dBV (emf) dBV (emf) dB dB dB
dB % % % mVRMS dBV
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TDA7421N
ELECTRICAL CHARACTERISTICS DC PARAMETERS (Tamb = 25C; VCC = 8V, Vdd = 5V, no RF input unless otherwise specified)
Symbol PLL VCC PLL ICC Parameter PLL Supply Voltage PLL Supply Current AM MODE FM MODE STBY MODE DIG Vdd DIG Idd Digital Supply Voltage Digital Supply Current AM MODE FM MODE STBY MODE RF VCC RF ICC RFSupply Voltage RF Supply Current AM MODE FM MODE STBY MODE IF1 VCC IF1 ICC IF1 Supply Voltage IF1 Supply Current AM MODE FM MODE STBY MODE IF2 VCC IF2 ICC IF2 Supply Voltage IF2 Supply Current AM MODE FM MODE STBY MODE OSC VCC OSC ICC Oscillator Supply Voltage Oscillator Supply Current AM MODE FM MODE STBY MODE Voltage Controlled Oscillator (VCO) Ref: FM Test Circuit, measure Vosc with high impedance FET probe fVCOmin fVCOmax Minimum VCO Frequency Maximum VCO Frequency Vtun = 0 Vtun = VCC Europe/USA Japan Europe/USA Japan 123.2 79.2 80.9 55 128 90 98.2 65.4 MHz MHz 7.5 17.0 81.0 10 7.5 10.0 28.0 10 7.5 4.0 22.0 10 V mA mA mA V mA mA mA V mA mA mA 7.5 27.0 13.0 10 4.75 4.6 4.0 5.25 Test Condition Min. 7.5 1.6 3.0 Typ. Max. 10 Unit V mA mA mA V mA mA mA V mA mA
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TDA7421N
ELECTRICAL CHARACTERISTICS (Continued)
Symbol VOSC C/N Parameter Oscillator Amplitude Test Condition fOSC = 108.8MHz, Europe/USA fOSC = 72.3MHz Japan 1KHz offset Min. Typ. 110 Max. Unit dBV
Carrier to Noise
85
dBc/Hz
Reference Oscillator Ref: AM Test Circuit, measureVXTAL with high impedance FET probe fXTAL VXTAL Reference Frequency Oscillator Amplitude 10.25 108 MHz dBV
FM Front-end Electrical Adjustments Ref: FM Test Circuit, measure VANTADJ and VRFADJ referred to VPLLOUT ANTADJ
MAX OFF
Maximum FM Antenna Filter Adjustment Voltage Offset FM Antenna Filter Adjustment Voltage Offset Step Maximum FM RF Filter Adjustment Voltage Offset FM RF Filter Adjustment Voltage Offset Step
VPLLOUT = 2.5V, ANA3-0 set to 1111 VPLLOUT = 2.5V, ANA3-0 set to 1001 VPLLOUT = 2.5V, RFA3-0 set to 1111 VPLLOUT = 2.5V, RFA3-0 set to 1001
21 2.8 21 2.8
25 3.6 25 3.6
27 4.4 27 4.4
% % % %
ANTADJ
STEP OFF
RFADJ
MAX OFF
RFADJ
STEP OFF
FM Mixer Ref: FM Test Circuit, measure input at VMIXFMIN, output at VMIXOUT RIN,MIX GMIX IP3MIX CP1MIX CAdj1 Single-ended input resistance (pin 3, pin4) Conversion Gain 3rd order intermodulation distortion intercept point 1dB compression point Value of the minimum adjusting capacitance step fIN = 98.1MHz fd = 98.1MHz; fu1 = 98.2MHz; fu2 = 98.3MHz; fIN = 98.1MHz T1A3-0 set to 1000 12 21.8 108 dB dBV
90 0.38
dBV pF
FM AGC Ref: FM Test Circuit, measure input at VFMRFAGCIN and VFMIFAGCIN, output at VFMAGCOUT VRFAGCSTART Open Loop RF AGC Starting Point fRFAGCIN = 98.1MHz Value of VFMRFAGCIN at which VFMAGCOUT = 4V 80 dBV
RIN,RFAGC VIFAGCTART
Input Resistance Open Loop IF AGC Starting Point fIFAGCIN = 10.7MHz Value of VFMIFAGCIN at which VFMAGCOUT = 4V FAGC2-0 set to 111
20 77
K dBV
RIN,IFAGC
Input Resistance
20 10
K K
ROUT,FMAGC Output Resistance
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TDA7421N
ELECTRICAL CHARACTERISTICS (Continued)
FM IF Amplifier 1 Ref: FM Test Circuit, measure input at VFMAMP1IN, output at VFMAMP1OUT Symbol RIN,AMP1 ROUT,AMP1 GAMP1 IP3AMP1 Parameter Input Resistance Output Resistance Typical Gain 3rd Order Intermodulation Distortion Intercept Point fIN = 10.7MHz fd = 10.7MHz; fu1= 10.8MHz; fu2= 10.9MHz; FBH3-0 set to 0100 fIN = 10.7MHz; FBH3-0 set to 0100 Test Condition Min. Typ. 330 330 18.5 Max. Unit dB dBV
CP1AMP1
1dB Compression Point
dBV
FM IF Amplifier 2 Ref: FM Test Circuit, measure input at VFMAMP2IN, output at VFMAMP2OUT RIN,AMP2 ROUT,AMP2 GMIN,AMP2 Input Resistance Output Resistance Minimum Gain f = 10.7MHz f = 10.7MHz fIN = 10.7MHz, FBL1-0 set to 01 fIN = 10.7MHz, FBL1-0 set to 00 fd = 10.7MHz; fu1= 10.8MHz; fu2= 10.9MHz; FBL3-0 set to 0100 fIN = 10.7MHz; FBL3-0 set to 0100 330 330 6 10 dB dB dBV
GMAX,AMP2 Maximum Gain IP3AMP2 3rd Order Intermodulation Distortion Intercept Point
CP1AMP2
1dB Compression Point
dBV
FM Limiter, Field Strengh Meter and Demodulator Ref: FM Test circuit, measure: - Input at VFMLIMIN, fIN = 10.7MHz - FS Meter output at VFMSMETER (FMADJ set to 0, FSL4-0 set to 00000) - demodulator adjustment output at VFSMETER (FMADJ set to 1) RIN,LIM GLIM LS SM1 SM2 SM3 SM4 Limiter Input Resistance Limiter Gain Limiting Sensitivity Smeter 1 Smeter 2 Smeter 3 Smeter 4 VFMLIMIN = 40dBV VFMLIMIN = 60dBV VFMLIMIN = 80dBV VFMLIMIN = 100dBV VFMLIMIN = 70dBV; FSL4-0 set to 00000 VFMLIMIN = 70dBV; FSL4-0 set to 11111 330 90 23 1.1 2.3 3.7 4.9 0.0 1.5 dB dBv V V V V V V
SMMINSHIFT Smeter Minimum Shift Voltage SMMAXSHIFT Smeter Maximum Shift Voltage
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TDA7421N
ELECTRICAL CHARACTERISTICS (Continued)
Symbol GDEM GDEMADJ CAdjDem Parameter Demodulator Conversion Gain Demodulator Adjustment Conversion Gain Value of the minimum adjusting capacitance step Test Condition VFMLIMIN > LS VFMLIMIN > LS DEM6-0 set to 0000001 Min. Typ. 2 14 50 Max. Unit mVRMS/ KHz mVRMS/ KHz fF
FM Audio Amplifier Ref: FM Test circuit, VFMLIMIN, = 95dBV, fIN = 10.7MHz; measure: - MPX output at VAUDIO, BPF 200Hz to 15KHz, 50s de-emphasis. - muting voltage at VMUTE, DRIVE VMUTE Mute Voltage VMUTE,DRIVE for which VAF = -11.5dB; AUM1-0 set to 11 VMUTE,DRIVE for which VAF = -1dB, AUM1-0 set to 11 VMUTE,DRIVE < VPLAY VMUTE,DRIVE > VMUTE; AUM1-0 set to 00 VMUTE,DRIVE > VMUTE; AUM1-0 set to 11 fDEV = 75KHz, FMOD = 1KHz, VMUTE,DRIVE < VMUTE fDEV = 40KHz, FMOD = 1KHz, VMUTE,DRIVE < VMUTE fDEV = 40KHz, FMOD = 1KHz, VMUTE,DRIVE < VMUTE AM modulation depht 30%, fMOD = 1KHz, with respect to FM modulated signal with fDEV = 40KHz, VMUTE,DRIVE < VMUTE 5 1 9 -5 -12.5 400 2 V
VPLAY GAMP,PLAY
Play Voltage
0.3
V
Audio Amplifier Gain in Play Conditions
dB dB dB mVRMS %
MUTEATTMIN Minimum Mute Attenuation MUTEATTMAX Maximum Mute Attenuation VAF THD AF Output Level
AF Total Harmonic distortion
0.3
S+N/N
AF Signal to Noise Ratio
80
dB
AMR
Amplitude Modulation Rejection
67
dB
AUDIOcurr MUTE Rout
Output Current Capability Mute Drive Output Resistance
mA K
FM QUALITY DETECTORS
Field Strength Detector Ref: FM Test Circuit, HDDIS and BWDIS set to 1, measure: - Input at VFMLIMIN, fIN = 10.7MHz, CW - output at VMUTE,DRIVE FSDMIN Field Strength Detector Minimum Threshold VFMLIMIN level at which VMUTE,DRIVE = VMUTE, FSM3-0 set to 0000 dBV
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TDA7421N
ELECTRICAL CHARACTERISTICS (Continued)
Symbol FSDMAX Parameter Field Strength Detector Maximum Threshold Test Condition VFMLIMIN level at which VMUTE,DRIVE = VMUTE, FSM3-0 set to 1111 Min. Typ. 67.5 Max. Unit dBV
Detuning Detector Ref: FM Test Circuit; HDDIS and SMDIS set to 1, measure: - Input at VFMLIMIN, CW - output at VMUTE,DRIVE DDSTART Detuning Detector Starting Point frequency shift from 10.7MHz at which VMUTE,DRIVE = VPLAY frequency shift from 10.7MHz + DDSTART at which VMUTE,DRIVE = VMUTE, BWM2-0 set to 100, SEEK set to 0 frequency shift from 10.7MHz + DDSTART at which VMUTE,DRIVE = VMUTE, BWM2-0 set to 001, SEEK set to 0 ratio of "reception" mode integration time constant inside the Detuning Detector with respect to "seek" mode 23 30 KHz KHz
DDSLOPE,MIN Detuning Detector Minimum Muting Slope
DDSLOPE,MAX Detuning Detector Maximum Muting Slope
10
KHz
DDTRC
Detuning Detector Time Constant Ratio
34/6
s/s
Adjacent Channel Detector Ref: FM Test Circuit; BWDIS and SMDIS set to 1, measure: - Input at VFMLIMIN: desired 10.7MHz, 95dBV CW; undesired 10.8MHz CW - output at VMUTE,DRIVE ACDMAX Adjacent Channel Quality Detector Maximum Sensitivity Threshold Adjacent Channel Quality Detector Minimum Sensitivity Threshold amplitude of undesired signal at which VMUTE,DRIVE = VMUTE, HDM4-0 set to 11111 amplitude of undesired signal at which VMUTE,DRIVE = VPLAY, HDM4-0 set to 00000 91 dBu
ACDMIN
94.8
dBu
Field Strength Station Detector Ref: FM Test Circuit; SEEK set to 1, HDDIS and BWDIS set to 1, measure: - Input at VFMLIMIN: desired 10.7MHz, CW - output at VFMSD FSSDMIN Field Strength Station Detector Minimum Threshold VFMLIMIN level at which VFMSD = 2.5V; FSS4-0 set to 00000 VFMLIMIN level at which VFMSD = 2.5V; FSS4-0 set to 11111 dBV
FSSDMAX
Field Strength Station Detector Maximum Threshold
dBV
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TDA7421N
ELECTRICAL CHARACTERISTICS (Continued)
Detuning Station Detector Ref: FM Test Circuit; SEEK set to 1, HDDIS and SMDIS set to 1, measure: - Input at VFMLIMIN, CW; - output at VFMSD Symbol DSD Parameter Detuning Station Detector Threshold Test Condition frequency shift from 10.7MHz at which VFMSD = 2.5V Min. Typ. 28 Max. Unit KHz
Adjacent Channel Station Detector Ref: FM Test Circuit; SEEK set to 1, HDDIS and SMDIS set to 1, measure: - Input at VFMLIMIN: desired 10.7MHz, 95dBV CW; undesired 10.8MHz CW - output at VFMSD ACSDMAX Adjacent Channel Detector Maximum Sensitivity Threshold Adjacent Channel Detector Minimum Sensitivity Threshold amplitude of undesired signal at which VFMSD = 2.5V, HDM4-0 set to 11111 amplitude of undesired signal at which VFMSD = 2.5V, HDM4-0 set to 00000 92.5 dBV
ACSDMIN
94.9
dBV
AM Mixer 1 Ref: AM Test Circuit, measure input at VMIX1AMIN, output at VMIXOUT RIN,MIX1 GMIX1 IP3MIX1 CP1MIX1 CAdj1 Input Resistance Conversion Gain 3rd Order Intermodulation Distortion Intercept Point 1dB Compression Point Value of the minimum adjusting capacitance step fIN = 1MHz fd = 1MHz; fu1 = 1.1MHz; fu2 = 1.2MHz fIN = 1MHz T1A3-0 set to 1000 1.2 7.6 131 K dB dBV
110 0.38
dBV pF
AM Wide & Narrow AGC Ref: AM Test Circuit; measure input at VMIX1AMIN and VMIX2AMIN, output at VAMAGC1AMP and VAMAGC1PIN VWAGCMIN Open Loop WIDE AGC Minimum Starting Point fWAGCIN = 999kHz, AAGW1-0 set to 11; VMIX1AMIN at which VAMAGC1AMP = 2.5V fWAGCIN = 999kHz, AAGW1-0 set to 00; VMIX1AMIN at which VAMAGC1AMP = 2.5V fNAGCIN = 10.7MHz, AAGN1-0 set to 11; VMIX2AMIN at which VAMAGC1AMP = 2.5V fNAGCIN = 10.7MHz, AAGN3-0 set to 00; VMIX2AMIN at which VAMAGC1AMP = 2.5V 95 dBV
VWAGCMAX
Open Loop WIDE AGC Maximum Starting Point
101
dBV
VNAGCMIN
Open Loop NARROW AGC Minimum Starting Point
81
dBV
VNAGCMAX
Open Loop NARROW AGC Maximum Starting Point
87
dBV
ROUTAMAGC1 Output Resistance IAMAGC1PIN Maximum Antenna Attenuation Diode Current fWAGCIN = 999kHz; VMIX1AMIN = 120dBV; AAGW1-0 set to 00
23.3 1.4
K mA
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TDA7421N
ELECTRICAL CHARACTERISTICS (Continued)
AM Mixer 2 Ref: AM Test Circuit; measure input at VMIX2AMIN, output at VMIX2OUT (switches must be in position 2 for AGC measurements). Symbol RIN,MIX2 GMIX2 IP3MIX2 CP1MIX2 CAdj2 AGCMIXSP Parameter Input Resistance Maximum conversion Gain 3rd Order Intermodulation Distortion Intercept Point 1dB Compression Point Value of the minimum adjusting capacitance step AGC2 Starting Point on Mixer 2 fIN = 10.7MHz fd = 10.7MHz; fu1 = 10.8MHz; fu2 = 10.9MHz fIN = 10.7MHz T2A3-0 set to 0001 fIN = 10.7MHz; Value of VMIX2AMIN for which VMIX2OUT is 1dB compressed; IF2A1-0 set to 10 fIN = 10.7MHz:VMIX2OUT for VMIX2AMIN = 1dB; IF2A1-0 set to 10 fIN = 10.7MHz; Range of VMIX2AMIN above AGCMIXSP for which VMIX2OUT is not increasing linearly with a 1dB/dB slope; IF2A1-0 set to 10 50 Test Condition Min. Typ. 5 25 117 Max. Unit K dB dBV
107 1.57 48
dBV pF dBV
AGCMIXIS
AGC2 intervention slope on Mixer 2
0.1
dB/dB
AGCMIXR
AGC2 Range on Mixer 2
dB
AM IF2 Amplifier Ref: AM Test Circuit; fIN = 450KHz, measure input at VIF2AMPIN, output at VIF2AMPOUT (switches must be in position 1). RIN,IF2AMP Input Resistance VIF2AMPIN = 10dBV; IF2A1-0 set to 00 VIF2AMPIN = 10dBV; IF2A1-0 set to 11 2 50 59 60 K dB dB dBV
GIF2AMPMIN Minimum Gain GIF2AMPMAX Maximum Gain
AGCAMPSP AGC2 Starting Point on IF2 Amp Value of VIF2AMPIN for which VIF2AMPOUT is 1dB compressed, IF2A1-0 set to 01 AGCAMPR AGC2 Range on IF2 Amp fIN = 10.7MHzRange of VIF2AMPIN above AGCAMPSP for which VIF2AMPOUT is not increasing linearly with a 1dB/dB slope; IF2A1-0 set to 01 fIN = 10.7MHz; VIF2AMPOUT for VIF2AMPIN = 1dB; IF2A1-0 set to 1 Ratio of AGC2 "reception" Time Constant and "seek" Time Constant
33
dB
AGCAMPIS
AGC2 intervention slope on IF2 Amp
0.1
dB/dB
AGCTCR
AGC2 Time Constant Ratio
150/5
s/s
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TDA7421N
ELECTRICAL CHARACTERISTICS (Continued)
Symbol IFAMST IFAMSTcurr Parameter AM IF2 Output Level at pin 28 Current Capability of pin 28 Test Condition VIF2AMPIN = 72dBmV; AMSTEREO set to 1 AMSTEREO set to 1 Min. Typ. 106 150 Max. Unit dBV A
AM Field Strength Meter and Field Strength Station Detector Ref: AM Test Circuit; fIN = 10.7MHz, measure input at VMIX2AMIN, outputs at VAMSMETER and at VAMSD (switches in position 2). AMSM1 AMSM2 AMSM3 AMSDMIN AMSDMAX AM Smeter 1 at VAMSMETER AM Smeter 2 at VAMSMETER AM Smeter 3 at VAMSMETER Station Detector Minimum Threshold Station Detector Maximum Threshold VMIX2AMIN = 40dBV VMIX2AMIN = 60dBV VMIX2AMIN = 80dBV VMIX2AMIN at which VAMSD = 2.5V; ASS3-0 set to 0000, SEEK set to 1 VMIX2AMIN at which VAMSD = 2.5V; ASS3-0 set to 1111, SEEK set to 1 1.4 3.4 4.8 27 V V V dBV dBV
IF Counter Output Ref: AM & FM Test Circuit, measure at pin 28 IFCFM FM IFC Sensitivity VFMLIMIN at which Vpin 28 = 2.5V, SEEK set to 1, EW2-0 set to 101, IFS2-0 set to 010 VIF2AMPIN at which Vpin 28 = 2.5V, SEEK set to 1, EW2-0 set to 011, IF2-0 set to 100, AMFM STBY1-0 set to 10 34 dBV
IFCAM
AM IFC Sensitivity
29
dBV
IFCcurrent
IFC Current Capability
150
A
SD output Impedance Measure output at VFMSD SDIMP,ON SDIMP,TS SD output impedance SDDIS set to 0 7 700 M
SD output impedance (Tri-State) SDDIS set to 1
Loop Filter Input/Output (LP_IN1, LP_IN2, LP_IN3, LP_OUT) -IIN IIN VOL VOH IOUT IOUT Input Leakage Current Input Leakage Current Output Voltage Low Output Voltage High Output Current Sink Output Current Source VIN = GND; PDout = Tristate VIN = VDD; PDout = Tristate IIN = -0.2mA; VCC = 8.5V IOUT = 0.2mA; VCC = 8.5V VPLL = 8.5V; Vout = 0.5 to 8V 8 10 10 -2 -2 0 0 2 2 0.5 A A V V mA mA
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ELECTRICAL CHARACTERISTICS (Continued)
I2C Bus Interface Symbol fSCL tAA tbuf tHD-STA tLOW tHIGH tSU-SDA tHD-DAT tSU-DAT tR tF tSU-STO tDH VIL VIH Parameter SCL Clock Frequency SCL Low to SDA Data Valid Time the Bus Must Be Free for the New Transmission START Condition hold Time Clock Low Period Clock High Period Start Condition Setup Time Data Input Hold Time Date Input Setup Time SDA & SCL Rise Time SDA & SCL Full Time Stop Condition Setup Time DATA OUT Time Input Low Voltage Input High Voltage 3 4.7 300 1 Test Condition Min. Typ. 100 300 4.7 4.0 4.7 4.0 4.7 0 250 Max. 500 Unit KHz ns s s s s s s ns s s s ns V V
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TDA7421N
Figure 1. AM Test Circuit
VMiXOUT 330 VAMAGC1RFAMP VMiX2AMIN VCC T3 VCC 1 2 2K
T2
64
IAMAGC1PIN 63
61
60
58
57
56
55
AGC W&N 1 VMIX1AMIN 15pF
AMSMETER
54
2 2K VXTAL 11 + 1M -
35 34
2 1 VIF2AMPIN
15pF
12 40 VAMSD 41 VAMSMETER
AGC2
DET
33
VIF2AMPOUT
31
32
D98AU910
Figure 2. FM Test Circuit
VMIXOUT VFMAMP1IN 330 VFMIFAGCIN VFMAMP1OUT VFMAMP2IN VFMAMP2OUT
T2 VTun VCC
10nF 10nF 10nF 10nF
330 10nF 10nF
10nF
330
VMiXFMIN 50
T1
3
61
60
59
53
52 330 +
51
50 330
49
48 330 + 46 10nF VFMLIMIN 10nF
330 4
VTun 5K V1 L2
VCC
330K 330
22pF
15pF
8 9 +
45
68pF 5 10nF VFMAGCOUT 10nF 14 VAMTADJ 15 VRFADJ 16 VPLLOUT 40 VFMSD 41 VSMSHIFT 39 VAUDIO 100K 42
VFMRFAGCIN
FM AGC
AUDIO DEMOD
-
38
6
L6 37 31 VMUTEDRIVE 10nF
D00AU1196
VSMFLT
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TDA7421N
1.0 FM SECTION Featuring a single conversion configuration, it comprises a multi-stage IF limiter whose gain is I 2C controlled and a quadrature demodulator with detuning and adjacent channel detectors. Signal meter and stop station functions are also supported 2.0 AM SECTION AM signal is converted by means of UP-DOWN configuration (IF1 = 10.7MHz, IF2 = 450KHz) and MW/LW bands are covered. 3.0 PLL SECTION Three operating modes are available:
PM0 0 1 0 1 PM1 0 0 1 1 Operating Mode Standby AM not used FM
They are user programmable with the mode PM registers. 3.1 Standby mode It stops all functions. This allows low current consumption without loss of information in all registers. The pin LPOUT is forced to 0V in power on. All data registers are set to FE (11111110). The oscillator does not run in standby mode. 3.2 FM and AM Operation The FM or AM signal applies to a 32/33 prescaler, which is controlled by a 5 bit counter (A). The 5 bit register (PC0 to PC4) controls this divider. The output of the prescaler connects to a 11 bit divider (B). The 11 bit register (PC5 to PC15) controls the divider 'B'. 3.2.1 THREE STATE PHASE COMPARATOR The phase comparator generates a phase error signal according to phase difference between fSYN and fREF. This phase error signal drives the charge pump current generator. 3.2.2 CHARGE PUMP CURRENT GENERATOR This stage generates signed pulses of current. The phase error signal decides the duration and polarity of those pulses.The current absolute values are programmable by A0, A1, A2 registers for high current and B0, B1 registers for low current. 3.2.3 LOW NOISE CMOS OP-AMP An internal voltage divider at pin VREF connects the positive input of the low noise Op-Amp.The charge pump output connects the negative input. This internal amplifier in cooperation with external components can provide an active filter. The negative input is switchable to three input pins (LPIN 1, LPIN 2 and LPIN 3), to increase the flexibility in application.This feature allows two separate active filters for different applications.A logical "1" in the LPIN 1/2 register activates pin LPIN 1, otherwise pin LPIN 2 is active. While the high current mode is activated LPIN 3 is switched on.
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TDA7421N
3.2.4 INLOCK DETECTOR The charge pump is switched in low current mode as the truth table and the related figure shows.
CURRHIGH 0 1 1 1 1 LOCKENA X 1 1 0 0 LOCK (by inlock detector) X 1 0 1 0 Charge PumpCurrent low current low current High current High current High current
The charge pump is forced in low current mode when a phase difference of 10-40 usec is reached. A phase difference larger than the programmed values will switch the charge pump immediately in the high current mode. Few programmable delays are available for inlock detection.
4.0 IF COUNTER SYSTEM FOR AM/FM The IF counter mode is controlled by IFCM register:
IFCM1 0 0 1 1 IFCM0 0 1 0 1 FUNCTION NOT USED FM MODE AM MODE NOT USED
A sample timer to generate the gate signal for the main counter is built with a 14 bit programmable counter to have the possibility to use any frequency. In FM mode a 6.25 KHz, in AM mode a 1KHz signal is generated. This counter is followed by an asynchronous divider to generate several sampling times. ADDRESS ORGANIZATION (PLL and IF Counter)
MSB FUNCTION PLL CHARGE PUMP LL COUNTER PLL COUNTER LL REF COUNTER LL REF COUNTER LL LOCK DETECT FC REF COUNTER FC REF COUNTER FC CONTROL C CONTROL SUBAD 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H BIT 7 BIT 6 BIT 5 B1 PC5 PC13 RC5 RC13 D3 IRC5 IRC13 IFS0 BIT 4 B0 PC4 PC12 RC4 RC12 D2 IRC4 IRC12 CF4 BIT 3 A3 PC3 PC11 RC3 RC11 D1 IRC3 IRC11 CF3 BIT 2 A2 PC2 PC10 RC2 RC10 D0 IRC2 IRC10 EW2 CF2 BIT 1 A1 PC1 PC9 RC1 RC9 PM1 IRC1 IRC9 EW1 CF1 LSB BIT 0 A0 PC0 PC8 RC0 RC8 PM0 IRC0 IRC8 EW0 CF0
LPIN1/2 CURRH PC7 PC15 RC7 RC15 LDENA IRC7 IFCM1 IFENA IFS2 PC6 PC14 RC6 RC14 IRC6 IFCM0 IFS1
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TDA7421N
4.1 Intermediate Frequency Main Counter (IFMC) This counter is a 13-21 bit synchronous autoreload down-counter. Four bits are programmable to have the possibility for an adjust to the frequency of the IF filter.The counter length is automatically adjusted to the chosen sampling time and the counter mode. At the start the counter will be loaded with a defined value which is an equivalent to the divider value (tsample fIF).If a correct frequency is applied to the IF counter frequency inputs IF-AM and IF-FM, at the end of the sampling time the main counter is changing its state from 0 to 1FFFFFH.This is detected by a control logic. The frequency range inside which a successful count results is detected is adjustable setting bits EW 0, 1, 2. 4.2 Up-down counter filter The information coming from the IF main counter control logic is shifted into a 5 bit up down counter circuit clocked by the sampling time signal. At the start (rising edge of the IFENA signal) the counter is set to 10H and the SSTOP signal is forced to "1".Only when the counter reaches the value 10H - step, SSTOP goes to "0".SSTOP will be "1" again, if the counter reaches the value 10h + step. Figure 3. Charge Punp Logic
CURR HIGH CHARGE PUMP CURRENT LOCKENA
LOCK
D96AU548
Figure 4. FM and AM operation (swallow mode)
2 I C bus
REF OSC IN
fosc
REGISTER R0 ...R15 DIVIDER :R I2C bus
fref fsyn
PD
REGISTER PC0 ...PC4 COUNTER A (O/I) PRESCALER 32/33 FM IN
I2C bus
AM IN
REGISTER PC5 ... P15 DIVIDER :B
D96AU545
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ttim = (IFRC + 1) / fosc tcnt = (CF + 1697) / fIF FM mode tcnt = (CF + 44) / fIF AM mode Counter result succeeded: ttim > tcnt - terr and ttim > tcnt + terr Counter result failed: ttim< tcnt + terr or ttim > tcnt - terr where: ttim = IF time cycle time tcnt = IF counter cycle time terr = discrimination window (controlled by the EW registers)
succeeded tcnt -tERR tcnt +tERR
D96AU551
failed
failed
ttim
The precision of the measurements is adjustable by controlling the discrimination window. This is adjustable by programming the control registers EW0...EW2. The measurement time per cycle is adjustable by setting the register IFS0 - IFS2. The center frequency of the discrimination window is adjustable by the control register "CF0" to "CF4". The available values are reported in databyte specification 5.0 I2C BUS INTERFACE 5.1 General Description The TDA7421N supports the I2C bus protocol. This protocol defines the devices sending data into the bus as transmitter and the receiving device as the receiver. The device that controls the transfer is a master and the device being controlled is the slave. The master will always initiates data transfer and provide the clock to transmit or receive operations. 5.2 Data Transition Data transition on the SDA line must only occur when the clock SCL is low. SDA transitions while SCL is high will be interpreted as START or STOP condition. 5.3 Start Condition A start condition is defined by a HIGH to LOW transition of the SDA line while SCL is at a stable HIGH level. This START condition must precede any command and initiate a data transfer onto the bus.The TDA7421N continuously monitors the SDA and SCL lines for a valid START and will not response to any command if this condition has not been met. 5.4 Stop condition A STOP condition is defined by a LOW to HIGH transition of the SDA while the SCL line is at a stable HIGH level. This condition terminate the communication between the devices and force's the bus interface of the TDA7421N into the initial condition.
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Figure 5. Phase Comparator
5.5 Acknowledge Indicates a successful data transfer. The transmitter will release the bus after sending 8 bit of data. During the 9th clock cycle the receiver will pull the SDA line to LOW level to indicate it has received the eight bits of data correctly. 5.6 Data transfer During data transfer the TDA7421N samples the SDA line on the leading edge of the SCL clock, Therefore, for proper device operation the SDA line must be stable during the SCL LOW to HIGH transition. 5.7 Device Addressing To start the communication between two devices, the bus master must initiate a start instruction sequence, followed by an eight bit word corresponding to the address of the device it is addressing. The most significant 6 bits of the slave address identify the device type. The TDA7421N device code is fixed as "110001". The next significant bit is used either to address the tuner section (1) or the PLL section (0) of the chip. Following a START condition the master sends slave address word; the TDA7421N will "acknowledge" after this first transmission and wait for a second word (the word address field).This 8 bit address field provides an access to any of the 8 internal addresses. Upon receipt of the word address the TDA7421N slave device will respond with an "acknowledge". At this time, all the following words transmits to the TDA7421N will be considered as data.The internal address will be automatically incremented. After each word receipt the TDA7421N will answer with an "acknowledge". The interface protocol comprises: - a subaddress byte - a sequence of data (N-bytes + acknowledge) - a stop condition (P) - a start condition (S) - a chip address byte
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CONTROL REGISTER FUNCTION
REGISTER NAME PC RC IRC IFCM EW IFENA CF IFS PM D LPIN1/2 A B LDENA CURRH FUNCTION Programmable Counter for VCO Frequency Reference Counter PLL Reference Counter IF IF Counter Mode Frequency Error Window Enable IF Counter Center Frequency IF Counter Sampling Time IF Counter Stby, FM, AM, AM swallow mode (PLL Mode) Programmable Delay for Lock Detector Loop Filter Input Select Charge Pump High Current Charge Pump Low Current Lock Detector Enable Set Current High
Figure 6. IF Counter Block Diagram
IFENA EW-REGISTER
IF-AM
11-21 BIT COUNTER
ZD
IF-FM
CF-REGISTER
UP/DOWN COUNTER
OSC
14 BIT COUNTER
3 BIT COUNTER
IFC-REGISTER
IFS-REGISTER
D97AU809
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Figure 7. I2C Bus Timing Diagram
tHIGH
tR
tLOW
tR
SCL
tSU-STA tHD-DAT tHD-STA tSD-DAT tSUBTOP
SDA IN
tAA tDH ttxt
SDA OUT
D95AU378
5.8 Frame Example For addressing the PLL part:
CHIP ADDRESS MSB S 1 1 0 0 0 1 0 LSB 0 ACK MSB T2 T1 T0 I SUBADDRESS LSB A3 A2 A1 A0 ACK MSB DATA 1 to DATA n LSB ACK P
D96AU549
for the TUNER part:
CHIP ADDRESS MSB S 1 1 0 0 0 1 1 LSB 0 ACK MSB 0 0 0 I SUBADDRESS LSB A3 A2 A1 A0 ACK MSB DATA 1 to DATA n LSB ACK P
D96AU550
ACK: S: P: I: T2, T1, T0: A3, A2, A1, A0:
Acknowledge Start Stop Page mode used in test mode (for PLL only, for TUNER addressing they must be 0) Mode selection
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TDA7421N
5.9 TUNER SUBADDRESS
MSB X X X I A3 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 A2 0 0 0 0 1 1 1 1 0 0 A1 0 0 1 1 0 0 1 1 0 0 LSB A0 0 1 0 1 0 1 0 1 0 1 STATUS FM STOP STATION/FM IF AGC FM SMETER SLIDER/ AM IF2 AMP AM AGC1/AM STOP STATION IFT1/IFT2 FRONT END ADJUSTMENT FM DEMOD ADJUSTMENT FM AUDIO MUTE GAIN/FM IF BUFFERS/ FM SOFT MUTE FM HOLE DETECTOR/FM DETUNING TUNER TESTING Page mode disabled Page mode enabled must be "0" FUNCTION
5.10 PLL SUBADDRESS
MSB T3 T2 T1 I A3 0 0 0 0 0 0 0 0 1 1 0 1 A2 0 0 0 0 1 1 1 1 0 0 A1 0 0 1 1 0 0 1 1 0 0 LSB A0 0 1 0 1 0 1 0 1 0 1 Charge pump control PLL counter 1 (LSB) PLL counter 2 (MSB) PLL reference counter 1 (LSB) PLL reference counter 2 (MSB) PLL lockdetector control and PLL mode select IFC reference counter 1 (LSB) IFC reference counter 2 (MSB) and IFC mode select IF counter control 1 IF counter control 2 Page mode disabled Page mode enabled FUNCTION
T1, T2, T3 are used for testing the PLL, in application mode they have to be "0".
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TDA7421N
6.0 PLL DATA BYTE SPECIFICATION 6.1 CHARGE PUMP CONTROL
MSB D7 D6 D5 D4 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 LPIN1/2 CURRH B1 B0 A3 A2 A1 A0 0 1 0 1 D2 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 High current = 0mA High current = 0.5mA High current = 1.0mA High current = 1.5mA High current = 2.0mA High current = 2.5mA High current = 3.0mA High current = 3.5mA High current = 4.5mA High current = 5.0mA High current = 5.5mA High current = 6.0mA High current = 6.5mA High current = 7.0mA High current = 7.5mA Low current = 0A Low current = 15A Low current = 100A Low current = 115A Select low Current Select high Current Select loop filter 1 Select loop filter 2 Subaddress = 00H FUNCTION
6.2 PLL COUNTER 1 (LSB)
MSB D7 0 0 0 D6 0 0 0 D5 0 0 0 D4 0 0 0 D3 0 0 0 D2 0 0 0 D1 0 0 1 LSB D0 0 1 0 LSB = 0 LSB = 1 LSB = 2 FUNCTION
all combinations allowed 1 1 1 1 PC7 1 1 1 1 PC6 1 1 1 1 PC5 1 1 1 1 PC4 1 1 1 1 PC3 1 1 1 1 PC2 0 0 1 1 PC1 0 1 0 1 PC0 LSB = 252 LSB = 253 LSB = 254 LSB = 255 Bit name Subaddress = 01H
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TDA7421N
6.3 PLL COUNTER 2 (MSB)
MSB D7 0 0 0 D6 0 0 0 D5 0 0 0 D4 0 0 0 D3 0 0 0 D2 0 0 0 D1 0 0 1 LSB D0 0 1 0 MSB = 0 MSB = 256 MSB = 512 FUNCTION
all combinations allowed 1 1 1 1 PC15 1 1 1 1 PC14 1 1 1 1 PC13 1 1 1 1 PC12 1 1 1 1 PC11 1 1 1 1 PC10 0 0 1 1 PC9 0 1 0 1 PC8 MSB = 64768 MSB = 65024 MSB = 65280 MSB = 65536 Bit name Subddress = 02H
Swallow mode: fvco/fsyn = LSB + MSB + 32 6.4 PLL REFERENCE COUNTER 1 (LSB)
MSB D7 0 0 0 D6 0 0 0 D5 0 0 0 D4 0 0 0 D3 0 0 0 D2 0 0 0 D1 0 0 1 LSB D0 0 1 0 LSB = 0 LSB = 1 LSB = 2 FUNCTION
all combinations allowed 1 1 1 1 RC7 1 1 1 1 RC6 1 1 1 1 RC5 1 1 1 1 RC4 1 1 1 1 RC3 1 1 1 1 RC2 0 0 1 1 RC1 0 1 0 1 RC0 LSB = 252 LSB = 253 LSB = 254 LSB = 255 Bit name Subaddress =03H
6.5 PLL REFERENCE COUNTER 2 (MSB)
MSB D7 0 0 0 D6 0 0 0 D5 0 0 0 D4 0 0 0 D3 0 0 0 D2 0 0 0 D1 0 0 1 LSB D0 0 1 0 MSB = 0 MSB = 256 MSB = 512 FUNCTION
all combinations allowed 1 1 1 1 RC15 1 1 1 1 RC14 1 1 1 1 RC13 1 1 1 1 RC12 1 1 1 1 RC11 1 1 1 1 RC10 0 0 1 1 RC9 0 1 0 1 RC8 MSB = 64768 MSB = 65024 MSB = 65280 MSB = 65536 Bit name Subddress = 04H
fOSC/fREF = LSB + MSB + 1
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6.6 LOCK DETECTOR & PLL MODE CONTROL
MSB D7 D6 D5 D4 D3 D2 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 LDENA D3 D2 D1 D0 PM1 PM0 0 1 0 1 0 1 0 1 LSB D0 0 1 0 1 PLL standby mode PLL AM not used PLL FM mode PD phase difference threshold 10ns PD phase difference threshold 20ns PD phase difference threshold 30ns PD phase difference threshold 40ns Not used in application mode Activation delay = 4 * fref Activation delay = 6 * fref Activation delay = 8 * fref No lock detector controlled chargepump Lock detector controlled chargepump Bit name Subaddress = 05H FUNCTION
6.7 IF COUNTER REFERENCE CONTROL 1 (LSB)
MSB D7 0 0 0 D6 0 0 0 D5 0 0 0 D4 0 0 0 D3 0 0 0 D2 0 0 0 D1 0 0 1 LSB D0 0 1 0 LSB = 0 LSB = 1 LSB = 2 FUNCTION
all combinations allowed 1 1 1 1 IRC7 1 1 1 1 IRC6 1 1 1 1 IRC5 1 1 1 1 IRC4 1 1 1 1 IRC3 1 1 1 1 IRC2 0 0 1 1 IRC1 0 1 0 1 IRC0 LSB = 252 LSB = 253 LSB = 254 LSB = 255 Bit name Subaddress = 06H
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TDA7421N
6.8 IF COUNTER REFERENCE CONTROL 2 (MSB) AND IF COUNTER MODE SELECT
MSB D7 0 0 0 D6 0 0 0 D5 0 0 0 D4 0 0 0 D3 0 0 0 D2 0 0 0 D1 0 0 1 LSB D0 0 1 0 MSB = 0 MSB = 256 MSB = 512 FUNCTION
all combinations allowed 1 1 1 0 0 1 1 IFCM1 0 1 0 1 IFCM0 IRC13 IRC12 IRC11 IRC10 IRC9 IRC8 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 MSB = 15616 MSB = 15872 MSB = 16128 NOT USED IN APPLICATION MODE IF counter FM mode IF counter AM mode not used Bit name Subaddress = 07H
fosc/ftim = LSB + MSB + 1 6.9 IF COUNTER CONTROL 1
MSB D7 D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 0 1 IFENA EW2 EW1 EW0 D1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 don't use don't use don't use EW delta f = 6.25KHz (FM); 1KHz (AM) EW delta f = 12.5KHz (FM); 2KHz (AM) EW delta f = 25KHz (FM); 4KHz (AM) EW delta f = 50KHz (FM); 8KHz (AM) EW delta f = 100KHz (FM); 16KHz (AM) IF counter disabled / stand by IF counter enabled Bit name Subaddress = 08H FUNCTION
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TDA7421N
6.10 IF COUNTER CONTROL 2
MSB D7 D6 D5 D4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 IFS2 0 0 1 1 0 0 1 1 IFS1 0 1 0 1 0 1 0 1 IFS0 CF4 CF3 CF2 CF1 CF0 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 fcenter = 10.60000MHz (FM) 448KHz (AM) fcenter = 10.60625MHz (FM) 449KHz (AM) fcenter = 10.61250MHz (FM) 450KHz (AM) fcenter = 10.61875MHz (FM) 451KHz (AM) fcenter = 10.62500MHz (FM) 452KHz (AM) fcenter = 10.63125MHz (FM) 453KHz (AM) fcenter = 10.63750MHz (FM) 454KHz (AM) fcenter = 10.64375MHz (FM) 455KHz (AM) fcenter = 10.65000MHz (FM) 456KHz (AM) fcenter = 10.65625MHz (FM) 457KHz (AM) fcenter = 10.66250MHz (FM) 458KHz (AM) fcenter = 10.66875MHz (FM) 459KHz (AM) fcenter = 10.67500MHz (FM) 460KHz (AM) fcenter = 10.68125MHz (FM) 461KHz (AM) fcenter = 10.68750MHz (FM) 462KHz (AM) fcenter = 10.69375MHz (FM) 463KHz (AM) fcenter = 10.70000MHz (FM) 464KHz (AM) fcenter = 10.70625MHz (FM) 465KHz (AM) fcenter = 10.71250MHz (FM) 466KHz (AM) fcenter = 10.71875MHz (FM) 467KHz (AM) fcenter = 10.72500MHz (FM) 468KHz (AM) fcenter = 10.73125MHz (FM) 469KHz (AM) fcenter = 10.73750MHz (FM) 470KHz (AM) fcenter = 10.74375MHz (FM) 471KHz (AM) fcenter = 10.75000MHz (FM) 472KHz (AM) fcenter = 10.75625MHz (FM) 473KHz (AM) fcenter = 10.76250MHz (FM) 474KHz (AM) fcenter = 10.76875MHz (FM) 475KHz (AM) fcenter = 10.77500MHz (FM) 476KHz (AM) fcenter = 10.78125MHz (FM) 477KHz (AM) fcenter = 10.78750MHz (FM) 478KHz (AM) fcenter = 10.79375MHz (FM) 479KHz (AM) tsample = 20.48ms (FM mode); 128ms (AM; MODE) tsample = 10.24ms (FM mode); 64ms (AM; MODE) tsample = 5.12ms (FM mode); 32ms (AM; MODE) tsample = 2.56ms (FM mode); 16ms (AM; MODE) tsample = 1.28ms (FM mode); 8ms (AM;MODE) tsample = 640ms (FM mode); 4ms (AM;MODE) tsample = 320ms (FM mode); 2ms (AM; MODE) tsample = 160ms (FM mode); 1ms (AM; MODE) bit name Subaddress = 09H FUNCTION
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7.0 TUNER DATA BYTE SPECIFICATION 7.1 ADDRESS ORGANIZATION (Tuner AM/FM)
MSbit FUNCTION STATUS FM STOP STATION/ FM IF AGC FM SMETER SLIDER/ AM IF2 AMP AM AGC1/AM STOP STATION IFT1/IFT2 FRONT END ADJUSTMENT FM DEMOD ADJUSTMENT FM AUDIO MUTE GAIN/FM IF BUFFERS/ FM SOFT MUTE FM HOLE DETECTOR/ FM DETUNING TUNER TESTING SUBAD B7 00H 01H 02H O3H 04H 05H 06H 07H N.U. FAG2 FSL4 ASS3 T2A3 ANA3 N.U. FSM3 B6 B5 B4 AM STEREO FSS4 FSL1 ASS0 T2A0 ANA0 DEM4 FSM0 B3 SEEK FSS3 FSL0 AAGN1 T1A3 RFA3 DEM3 FFBL1 B2 AM/FM/ STBY FSS2 IF2A1 AAGN0 T1A2 RFA2 DEM2 FBL0 B1 AM/FM/ STBY FSS1 IF2A0 AAGW1 T1A1 RFA1 DEM1 AUM1 B0 AM/FM/ STBY FSS0 N.U. AAGW0 T1A0 RFA0 DEM0 AUM0 FMMUTE FMADJ FAG1 FSL3 ASS2 T2A2 ANA2 DEM6 FSM2 FAG0 FSL2 ASS1 T2A1 ANA1 DEM5 FSM1 LSbit
08H 09H
BWM2 PLLTEST
BWM1 T2
BWM0 T1
HDM4 T0
HDM3 SDDIS
HDM2 BWDIS
HDM1 HDDID
HDM0 SMDIS
7.2 STATUS (subaddress 00H)
MSB S6 FMMUTE S5 FMADJ S4 AMSTEREO S3 SEEK S2 AM/FM/ STBY 0 0 0 1 1 0 1 0 1 0 1 1 1 AM AM FM FM AM AM FM FM AM AM FM FM S1 AM/FM/ STBY 0 0 1 1 0 LSB S0 AM/FM/ STBY 0 1 0 0 0 Stand by FM on AM on (/6) AM on (/10) AM on (/8) RECEPTION SEEK AM IFC Out AM Stereo OUT FM on for demodulator adjustment, demod on FM on for demodulator adjustment, demod muted FUNCTION
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7.3 FM STOP STATION / FM IF AGC (subaddress 01H)
MSB FAG2 FM ifagc MSB FM ifagc FAG1 FM ifagc LSB FAG0 FSS4 FSS3 FSS2 LSB FSS1 FSS0 FUNCTION
FM STOP STATION THRESHOLD FM FM FM FM FM stopstation stopstation stopstation stopstation stopstation MSB LSB 0 X 1 0 X 1 0 X 1 0 X 1 0 X 1 Minimum sensitivity Maximum sensitivity
all combinations allowed FM IF AGC THRESHOLD 0 X 1 1 0 X 1 1 0 X 0 1 Minimum sensitivity Keyed AGC disabled Maximum sensitivity
all combinations allowed
7.4 FM SMETER SLIDER\IF2 AMPLIFIER (subaddress 02H)
MSB FSL4 FSL3 FSL2 FSL1 FSL0 IF2A1 AM if2Amp MSB IF2A0 AM if2Amp LSB FM SMETERSLIDING (mV) LSB FUNCTION
FMsmeter FMsmeter FMsmeter FMsmeter FMsmeter slider slider slider slider sliderr MSB LSB 0 0 X 1 0 0 X 1 0 0 X 1 0 0 X 1 0 1 X 1
0 48
1500
all combinations allowed IF2 AMPLIFIER GAIN 0 0 1 1 0 1 0 1 50dB 53dB 56dB 59dB
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7.5 AM STOP STATION / AM AGC1 (subaddress 03H)
MSB ASS3 ASS2 ASS1 ASS0 AAGN1 AAGN0 AAGW1 LSB AAGW0 FUNCTION
AM AMnagc AMnagc AMwagc AMwagc AM WAGC THRESHOLD AM AM AM stopstation stopstation stopstation stopstation MSB LSB MSB LSB MSB LSB 0 X 1 0 X 1 Maximum sensitivity Minimum sensitivity
all comb. allowed AM NAGC THRESHOLD 0 X 1 0 X 1 Maximum sensitivity Minimum sensitivity
all comb. allowed AM STOP STATION THRESHOLD 0 X 1 0 X 1 0 X 1 0 X 1 Minimum sensitivity Maximum sensitivity
all combinations allowed
7.6 IFT1/IFT2 (subaddress 04H)
MSB T2A3 T2A2 T2A1 T2A0 T1A3 T1A2 T1A1 LSB T1A0 FUNCTION
IFT2adju IFT2adju IFT2adju IFT2adju IFT1adju IFT1adju IFT1adju IFT1adju ADJUSTMENT CAPACITOR st MSB st st st LSB st MSB st st st LSB 0 0 1 1 1 1 0 1 0 1 1 1 0 1 1 0 1 1 0 1 0 1 0 1 15Cift1 8Cift1 4Cift1 2Cift1 Cift2 ( = 380pF) 0
all combinations allowed 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 1 0 1 0 0 0 1 0 Cift1 ( = 1.57pF) 2Cift2 4Cift2 8Cift2 15Cift2
all combinations allowed
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TDA7421N
7.7 FRONT END ADJUSTMENT (subaddress 05H)
MSB ANA3 ANT adjustm ANA2 ANT adjustm MSB ANA1 ANT adjustm ANA0 ANT adjustm LSB RFA3 RFA2 RFA1 RF adjustm 0 0 1 0 1 0 1 0 1 LSB RFA0 Voffset RF varicap / VPLL RF adjustm LSB 0 1 0 0 1 1 0 0 1 0 -3.6% -7.2% -14.3% -25% 3.6% 7.2% 14.3% 25% FUNCTION
RF RF adjustm adjustm MSB X 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1
all combinations allowed Voffset antenna varicap / VPLL X 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 0 -3.6% -7.2% -14.3% -25% 3.6% 7.2% 14.3% 25%
all combinations allowed
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TDA7421N
7.8 FM DEMODULATOR ADJUSTMENT (subaddress 06H)
MSB DEM6 demadj MSB 0 0 0 0 0 0 0 1 1 DEM5 demadj 0 0 0 0 0 0 1 0 1 DEM4 demadj 0 0 0 0 0 1 0 0 1 DEM3 demadj 0 0 0 0 1 0 0 0 1 DEM2 demadj 0 0 0 1 0 0 0 0 1 DEM1 demadj 0 0 1 0 0 0 0 0 1 LSB DEM0 demadj ADJUSTMENT CAPACITOR LSB 0 1 0 0 0 0 0 0 1 0 Cdemod (= 50fF) 2Cdemod 4Cdemod 8Cdemod 16Cdemod 32Cdemod 64Cdemod 127Cdemod FUNCTION
all combinations allowed
7.9 FM SOFT MUTE / FM IF AMPLIFIER/FM AUDIO MUTE GAIN (subaddress 07H)
MSB FSM3 FSM2 FSM1 FSM0 FBL1 buff2 gain FBL0 buff2 gain AUM1 Mute Depth MSB LSB AUM0 Mute Depth LSB FM SOFT MUTE THRESHOLD FUNCTION
FM FM FM FM softmute softmute softmute softmute MSB LSB 0 X 1 0 X 1 0 X 1 0 X 1
Maximum sensitivity
Minimum sensitivity
all combinations allowed Audio max mute attenuation 0 0 1 1 0 1 0 1 -5 -7.5 -10 -12.5
all comb. allowed Buffer 2 Gain (dB) 0 0 1 0 1 0 10 6 8
all else not allowed
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7.10 FM HOLE DETECTOR / FM DETUNING DETECTOR (subaddress 08H)
MSB BWM2 BW Slope 30kHz BWM1 BW Slope 15kHz BWM0 BW Slope 10kHz HDM4 HDM3 HDM2 HDM1 LSB HDM0 FUNCTION
Hole det Hole det Hole det Hole det Hole det MUTING SENSITIVITY(hole depth) MSB LSB 0 X 1 0 X 1 0 X 1 0 X 1 0 X 1 Maximum (shallow hole) Minimum (deep hole)
all combinations allowed RECEPTION 0 0 1 0 1 0 all else not allowed SEEK 0 0 X 1 0 1 X 1 X 0 X 1 Slower Clamping Window (4KHz over Threshold) CLAMPING WINDOW Not allowed Faster Clamping Window (1KHz over Threshold) 1 0 0 DETUNING MUTE RANGE (KHz) 10 15 30
all combinations allowed
7.11 TUNER TESTING (subaddress 9H)
MSB PLL TEST Test mode PLL 0 T2 Test mode MSB 0 T1 Test mode 0 T0 Test mode LSB 0 SDDIS SD output Disable 0 BWDIS HDDIS LSB SMDIS Soft Mute Disable 0 no test TEST MODES 1 1 0 1 1 0 1 1 all else not allowed 0 1 1 1 Soft Mute Test Hole Detector Test Bandwidth Test Audio Mute and SD Disabled FUNCTION
Bandwid Hole th detector Disable Disable 0 0
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7.11 TUNER TESTING (subaddress 9H)
MSB 0 0 0 1 1 0 1 1 0 1 all else not allowed 1 PLL Test 1 0 1 0 0 LSB FUNCTION AMSSDAC Test FMSSDAC Test FMSMDAC Test FMHDDAC Test FMIFAGCDAC Test
8.0 COMPONENT DESCRIPTION
CF1 CF3-CF4 CF2 Ceramic filter 10.7MHz, 180KHz BW Ceramic filter 10.7MHz, 150KHz BW Ceramic filter 450KHz, 6KHz BW FM RF transformer Unloaded Q= 69 3-1= 3 3/4T - 6-4= 3T 0.12f2UEW CTUNING(3-1)= 26.6pF @ 100MHz AM/FM IF1 transformer Unloaded Q= 70 1-3= 12T - 1-5= 6 - 5-3= 6 - 4-6= 2T 0.08f2UEW CINT(1-3) = 51pF; CEXT(1-3) = 5pF AM IF2 transformer Unloaded Q= 40 1-3= 178T - 1-2= 89T - 2-3= 89T - 4-6= 33T 0.05f2UEW CINT(1-3) = 180pF; CEXT(1-3) = 20pF Oscillator coil Unloaded Q= 8 06-4= 2 1/2T 0.12f2UEW CTUNING(6-4)= 36.8pF @ 100MHz Demodulator Coil Unloaded Q= 35 6-4= 27T 0.1f2UEW CINT(4-6)= 47pF; CEXT(4-6) = 13.5pF
2.7K 18nF
T1
T2
T3
L2
L6
AM BPF RC
27nF
D98AU915
100K
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TDA7421N
DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.40 0.05 1.35 0.18 0.12
mm TYP. MAX. 1.60 0.15 1.40 0.23 0.16 12.00 10.00 7.50 0.50 12.00 10.00 7.50 0.60 1.00 0(min.), 7(max.) 0.75 1.45 0.28 0.20 0.002 0.053 0.007 MIN.
inch TYP. MAX. 0.063 0.006 0.055 0.009 0.057 0.011
OUTLINE AND MECHANICAL DATA
0.0047 0.0063 0.0079 0.472 0.394 0.295 0.0197 0.472 0.394 0.295 0.0157 0.0236 0.0295 0.0393
TQFP64
D D1 A D3 A1 48 49 33 32
0.10mm Seating Plane
A2
B
E3
E1
64 1 e 16
17 C
L1
E
L
K
TQFP64
B
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TDA7421N
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (R) 2000 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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